DRAM PM
The DRAM (Dynamic RAM) is the most common type of memory at the start of this millennium. This is a memory whose transistors are arranged in a matrix in rows and columns. A transistor, coupled with a capacitor, gives information on a bit. Since 1 octet contains 8 bits, a DRAM memory module of 256 Mo will thus contain 256 * 2^10 * 2^10 = 256 * 1024 * 1024 = 268,435,456 octets = 268,435,456 * 8 = 2,147,483,648 bits = 2,147,483,648 transistors. A module of 256 Mo thus has a capacity of 268,435,456 octets, or 268 Mo! These memories have access times of 60 ns.
Furthermore, access to memory generally concerns data stored consecutively in the memory. Thus burst mode allows access to the three pieces of data following the first piece with no additional latency time. In this burst mode, time required to access the first piece of data is equal to cycle time plus latency time, and the time required to access the other three pieces of data is equal to just the cycle time; the four access times are thus written in the form X-Y-Y-Y, for example 5-3-3-3 indicates a memory for which 5 clock cycles are needed to access the first piece of data and 3 for the subsequent ones.
DRAM FPM
To speed up access to the DRAM, there is a technique, known as paging, which involves accessing data located in the same column by changing only the address of the row, thus avoiding repetition of the column number between reading of each row. This is known as DRAM FPM (Fast Page Mode). FPM achieves access times of around 70 to 80 nanoseconds for operating frequency between 25 and 33 Mhz.
DRAM EDO
DRAM EDO (Extended Data Out, sometimes also called hyper-page") was introduced in 1995. The technique used with this type of memory involves addressing the next column while reading the data in a column. This creates an overlap of access thus saving time on each cycle. EDO memory access time is thus around 50 to 60 nanoseconds for operating frequency between 33 and 66 Mhz.
Thus the RAM EDO, when used in burst mode, achieves 5-2-2-2 cycles, representing a gain of 4 cycles on access to 4 pieces of data. Since the EDO memory did not work with frequencies higher than 66 Mhz, it was abandoned in favour of the SDRAM.
SDRAM
The SDRAM (Synchronous DRAM), introduced in 1997, allows synchronised reading of data with the mother-board bus, unlike the EDO and FPM memories (known as asynchronous) which have their own clock. The SDRAM thus eliminates waiting times due to synchronisation with the mother-board. This achieves a 5-1-1-1 burst mode cycle, with a gain of 3 cycles in comparison with the RAM EDO. The SDRAM is thus able to operate with frequency up to 150 Mhz, allowing it to achieve access times of around 10 ns.
DR-SDRAM (Rambus DRAM)
The DR-SDRAM (Direct Rambus DRAM) is a type of memory that lets you transfer data to a 16-bit bus at frequency of 800Mhz, giving it a bandwidth of 1.6 Go/s. As with the SDRAM, this type of memory is synchronised with the bus clock to enhance data exchange. However, the RAMBUS memory is a proprietary technology, meaning that any company wishing to produce RAM modules using this technology must pay royalties to both RAMBUS and Intel.
DDR-SDRAM
The DDR-SDRAM (Double Data Rate SDRAM) is a memory, based on the SDRAM technology, which doubles the transfer rate of the SDRAM using the same frequency.
Data are read or written into memory based on a clock. Standard DRAM memories use a method known as SDR (Single Data Rate) involving reading or writing a piece of data at each leading edge.
